Pipeline CPU Simulator
Step through a five-stage pipeline one cycle at a time, with hazards, forwarding and stall bubbles drawn onto the diagram as they happen.
a diagramevery cycle
The problem
Architecture lectures draw the pipeline as one static diagram, and everything that is actually hard about it happens between the cycles that diagram never shows.
Overview
Educational simulator that makes the classic five-stage pipeline tangible. Advance one cycle at a time and watch instructions flow through fetch, decode, execute, memory and writeback, with data, structural and control hazards marked on the diagram at the moment they occur.
The pipeline state is fully observable: every register, every forwarding bypass and every stall bubble is visible at every cycle, so you can stop anywhere and read off exactly what the hardware is doing rather than reconstructing it from a lecture slide.
What it does
- 01Cycle-accurate view of a five-stage MIPS-style pipeline
- 02Step forward, pause and inspect any cycle
- 03Data, structural and control hazards marked as they arise
- 04Forwarding paths and stall bubbles drawn onto the diagram
- 05Register file and memory state updated live each cycle
- 06Loadable instruction sequences for the classic teaching examples